1. Field of Invention
The present invention relates to an image processing circuit as well as an image data processing method suited for application to an electrooptic device, wherein video signals obtained by dividing a video signal into a plurality of channels and extending the time axis thereof, so as to maintain a predetermined signal level every unit time, are fed to corresponding data lines at a predetermined timing. Also, it relates to an electrooptic device and electronic equipment which employ such a processing circuit or method.
2. Description of Related Art
A conventional electrooptic device, for example, an active matrix-type liquid-crystal display device, will be explained with reference to FIGS. 11 and 12. First, as shown in FIG. 11, the conventional liquid-crystal display device is constructed of a liquid-crystal display panel 100, a timing circuit 200, and a video signal processing circuit 300. The timing circuit 200 outputs timing signals for use in various portions. The video signal processing circuit 300 can include a D/A converter circuit 301 that converts image data Da supplied by external equipment from a digital signal into an analog signal and outputs the resulting signal as a video signal VID. Further, a phase expansion circuit 302 can be included that expands the received video signal VID of one channel into video signals of N phases (N=6 in the figure) and outputs the resulting video signals. Here, the video signal is expanded into N phases by a sampling circuit so that a time period for which the video signal fed to thin film transistors (TFTs) is applied is lengthened, thereby sufficiently securing a sampling time period for the data signals and a charge/discharge time period for the TFT panel 100 for the data signals.
In turn, an amplifier/inverter circuit 303 subjects the video signals to polarity inversion under the following conditions and amplifies the inverted signals as required, so as to feed phase-expanded video signals VID1-VID6 to the liquid-crystal display panel 100. Here, xe2x80x9cpolarity inversionxe2x80x9d signifies alternately inverting the voltage levels of the video signals with respect to a reference potential set at the center potential of the amplitudes of the video signals. Besides, the inversion of the video signals is done when the method of applying the data signal is (1) polarity inversion in scanning line units, (2) polarity inversion in data signal line units, or (3) polarity inversion in pixel units, and the inversion period is set at one horizontal scanning period or one dot clock period.
The liquid-crystal display panel 100 can be constructed so that an element substrate and a counter substrate are opposed to each other with a gap defined therebetween, and a liquid crystal is enclosed in the gap. Here, each of the element substrate and the counter substrate can be made of a quartz substrate, a hard glass, or the like.
In the element substrate, a plurality of scanning lines 112 are arrayed and formed in parallel so as to extend in the X-direction in FIG. 12, while a plurality of data lines 114 are formed in parallel so as to extend in the Y-direction orthogonal to the scanning lines 112. Here, the data lines 114 are divided into blocks each consisting of six lines, and the blocks are termed xe2x80x9cblocks B1-Bmxe2x80x9d. For brevity of the ensuing explanation, when referring to the data lines in general, they will be designated by the reference numeral 114, but when referring to specified ones of the data lines 114, they will be designated by reference numerals 114a-114f. 
At the intersection points between the scanning lines 112 and the data lines 114, TFTs 116 are connected as switching elements, by way of example. More specifically, the gate electrodes of the TFTs 116 are connected to the scanning lines 112, while the source electrodes thereof are connected to the data lines 114, and the drain electrodes thereof are connected to pixel electrodes 118. Individual pixels are configured of the pixel electrodes 118, a common electrode formed on the counter substrate, and the liquid crystal sandwiched in between both the electrodes, and they are arrayed in the shape of a matrix at the intersection points between the scanning lines 112 and the data lines 114. Incidentally, retention capacitors (not shown) are further formed in a state where they are respectively connected to the pixel electrodes 118.
Meanwhile, a scanning line driver circuit 120 can be formed on the element substrate, and the scanning line driver circuit 120 outputs pulse-like scanning signals to the respective scanning lines 112 in succession on the basis of a clock signal CLY, the inverted clock signal CLYinv thereof, a transfer start pulse DY, etc. delivered from the timing circuit 200. More specifically, the scanning line driver circuit 120 successively shifts the transfer start pulse DY fed at the beginning of a vertical scanning period in accordance with the clock signal CLY and the inverted clock signal CLYinv, and it outputs the resulting signals as scanning line signals, to thereby successively select the respective scanning lines 112.
On the other hand, a sampling circuit 130 includes a sampling switch 131 at one end of each of the data lines 114. The switches 131 can be made of TFTs which are also formed on the element substrate, and the source electrodes of these switches 131 are fed with the corresponding video signals VID1-VID6 through video signal feed lines L1-L6. Besides, the gate electrodes of the six switches 131 connected to the data lines 114a-114f of the block B1 are connected to a signal line which is fed with a sampling signal S1, and those of the six switches 131 connected to the data lines 114a-114f of the block B2 are connected to a signal line which is fed with a sampling signal S2. Likewise, the gate electrodes of the six switches 131 connected to the data lines 114a-114f of the block Bm are connected to a signal line which is fed with a sampling signal Sm. Here, each of the sampling signals S1-Sm is a signal for sampling the video signals VID1-VID6 every block within a horizontal effective display period.
A shift register circuit 140 is also formed on the element substrate, and the shift register 140 outputs the sampling signals S1-Sm in succession on the basis of a clock signal CLX, the inverted clock signal CLXinv thereof, a transfer start pulse DX, etc. delivered from the timing circuit 200. More specifically, the shift register circuit 140 successively shifts the transfer start pulse DX fed at the beginning of the horizontal scanning period in accordance with the clock signal CLX and the inverted clock signal CLXinv, and it successively outputs the resulting signals as the sampling signals S1-Sm.
In such a construction, when the sampling signal S1 is outputted, the video signals VID1-VID6 are respectively sampled by the six data lines 114a-114f belonging to the block B1, and they are respectively written into the six pixels associated with the selected scanning lines at the current time by the corresponding TFTs 116.
Thereafter, when the sampling signal S2 is outputted, the video signals VID1-VID6 are respectively sampled by the six data lines 114a-114f belonging to the block B2, on this occasion, and they are respectively written into the six pixels associated with the selected scanning lines at that time by the corresponding TFTs 116.
Likewise, when the sampling signals S3, S4, . . . and Sm are successively outputted, the video signals VID1-VID6 are respectively sampled by the six data lines 114a-114f belonging to the blocks B3, B4, . . . and Bm, and they are respectively written into the six pixels associated with the selected scanning lines at those times. Then, the next scanning lines are subsequently selected, and similar write operations are repeatedly executed in the blocks B1-Bm.
With the above driving system, the number of stages of the shift register circuit 140 for driving and controlling the switches 131 in the sampling circuit 130 is reduced to ⅙ as compared with the number of stages in a system in which the respective data lines are driven in point sequence. Moreover, the frequencies of the clock signal CLX and the inverted clock signal CLXinv to be fed to the shift register circuit 140 may be as small as ⅙, so that a lower power dissipation can be attained along with a reduction in the number of stages.
However, in the system in which a video signal of one channel is subjected to phase expansion into a plurality of channels so as to drive a liquid-crystal display panel by employing multi-channel video signals, there can be a problem in that gradations to be displayed deviating from the desired ones are displayed in block units (hereinbelow, the phenomenon shall be termed xe2x80x9cblock ghostxe2x80x9d).
By way of example, consider a liquid-crystal display panel which operates in a normally-white mode, and one screen of which is constituted by blocks B1-B7, as shown in FIG. 13A. It is assumed that black is displayed in the blocks B1-B3 and in the area b41 of the block B4, as shown in FIG. 13B, while a gray level is displayed in the area b42 of the block B4 and in the blocks B5, B6 and B7. Then, the area b42 becomes somewhat brighter than the gray level, and the following block B5 becomes somewhat darker than the gray level.
As a result of repeated experiments and studies on such block ghosts, it has been found that the major factors of the block ghost are the two factors stated below.
In the liquid-crystal display panel 100 shown in FIG. 12, an equivalent circuit concerning the i-th block Bi is as shown in FIG. 14. Referring to FIG. 14, letter R indicates the equivalent resistance of the counter electrode (common electrode). Since the liquid crystal is sandwiched between the video signal feed lines L1-L6 and the counter electrode, parasitic capacitances appear. Reference characters Cxa-Cxf denote the parasitic capacitances as equivalent capacitances. Further, reference characters 131a-131f denote the sampling switches 131 which correspond to the respective video signal feed lines L1-L6. In addition, reference characters Cya-Cyf denote the parasitic capacitances of the data lines 114a-114f (chiefly appearing between these data lines and the counter electrode) and the capacitances of pixel capacitors as equivalent capacitances.
The first factor consists in the point that differentiator circuits are formed by the equivalent capacitances Cxa-Cxf and the resistance R, so when the video signals VID1-VID6 are inputted to the liquid-crystal display panel 100, a waveform corresponding to the magnitude of the voltage changes of the video signals VID1-VID6 is generated on the counter electrode.
The second factor is that voltage change of the counter electrode is due to charging/discharging in the case where the block Bi is selected. More specifically, when the block Bi is selected to turn ON the switches 131a-131f, the equivalent capacitances Cya-Cyf are charged/discharged from an initial voltage Vs (the voltage at the nodes between the equivalent capacitances Cya-Cyf and the switches 113a-113f at the start of the selection time period of the block Bi) to the voltages of the video signals VID1-VID6. The second factor results from a differential waveform being generated on the counter electrode by charging/discharging currents on this occasion.
The voltage distortions of the differential waveforms caused by the first and second factors appear at the start of the selection time period of the block Bi, and attenuate over time. Letting Ve denote an error voltage which remains on the counter electrode at the end of the selection time period of the block Bi, non-uniformity in display occurs unless Ve is set to zero. The reason is that the switches 113a-113f are turned OFF at the end of the selection time period, so voltages affected by the error voltage Ve are held in the pixel capacitors.
A first error voltage Ve1 attributable to the first factor is given by the following equation (1), where xcex1 denotes a constant, and Vk,i denotes the video signal which is to be fed to the k-th data line in the i-th block:                     Ve1        =                  α          ⁢                                    ∑                              k                =                1                            6                        ⁢                          (                                                V                                      k                    ,                    t                                                  -                                  V                                      k                    ,                                          i                      -                      1                                                                                  )                                                          (        1        )            
A second error voltage Ve2 attributable to the second factor is given by the following equation (2), where xcex2 denotes a constant:                     Ve2        =                  β          ⁢                                    ∑                              k                =                1                            6                        ⁢                          (                                                V                                      k                    ,                    1                                                  -                Vs                            )                                                          (        2        )            
Accordingly, the error voltage Ve which is the total of the error voltages Ve1 and Ve2 is given by the following equation (3):                     Ve        =                              α            ⁢                                          ∑                                  k                  =                  1                                6                            ⁢                              (                                                      V                                          k                      ,                      i                                                        -                                      V                                          k                      ,                                              i                        -                        1                                                                                            )                                              +                      β            ⁢                                          ∑                                  k                  =                  1                                6                            ⁢                              (                                                      V                                          k                      ,                      i                                                        -                  Vs                                )                                                                        (        3        )            
Using equations (1)-(3), luminance changes in the blocks B3 to B5 shown in FIG. 13B will be studied. Here, as shown in FIG. 13B, it is assumed that a black level Vb is fed to the four left-hand data lines (in the area b41) among the six data lines 114a-114f constituting the block B4, that a gray level Vc is fed to the two right-hand data lines (in the area b42), and that the initial voltage Vs agrees with the gray level Vc.
First, consider the change of the luminance level of the block B3 at I=3. As shown in FIG. 13A, the block B2 directly preceding the block B3 displays black similarly to the block B3. Therefore, both the terms Vk,i and Vk,ixe2x88x921 in equation (1) become the black level Vb, and Ve1=0 holds. Since the initial voltage Vs agrees with the gray level Vc, Ve2=6xcex2(Vbxe2x88x92Vc) greater than 0 holds. Accordingly, the error voltage Ve becomes positive, and the block B3 brightens. Human vision, however, cannot substantially detect a luminance change for black though it can detect even a slight luminance change for a gray level. Therefore, a person would hardly notice that the block B3 has become brighter.
Secondly, regarding the block B4, black is displayed in the ⅔ area b41, and a gray level is displayed in the remaining ⅓ area b42. Therefore, Ve1=xe2x88x922xcex1(Vbxe2x88x92Vc) less than 0 and Ve2=4xcex2(Vbxe2x88x92Vc) greater than 0 hold. Whether the error voltage Ve takes a positive value or a negative value, depends upon the values of the constants xcex1 and xcex2. In general, the values of the equivalent capacitances Cya-Cyf are greater than those of the equivalent capacitances Cxa-Cxf, so that xcex2 greater than xcex1 holds in many cases. Accordingly, the error voltage Ve usually becomes positive, and the entire block B4 brightens. Owing to the visual characteristic stated above, however, a person can detect that the area b42 displaying the gray level has brightened, though they hardly notices that the luminance of the area b41 displaying black has increased.
Thirdly, since the gray level is displayed in the block B5, Ve1=xe2x88x924xcex1(Vbxe2x88x92Vc) less than 0 and Ve2=0 hold, and the error voltage Ve takes a negative value. Therefore, the block B5 darkens.
The present invention has been made in view of the above circumstances, and has one object to strongly enhance the display quality in such a way that, in a case where a gray level to be displayed changes midway in a block, block ghosting in the remaining area (for example, b42) of the pertinent block and in the next block (for example, B5) are cancelled.
In order to accomplish the object, an image processing circuit according to a first aspect of the present invention is an image processing circuit for use in an electrooptic device having a plurality of scanning lines, a plurality of data lines, switching elements which are respectively disposed in correspondence with intersections between the scanning lines and the data lines, and pixel electrodes which are electrically connected to the corresponding switching elements. The image processing circuit can include a delay circuit which delays externally supplied image data by a unit time so as to output delayed image data, a first correction-data generation circuit for generating first correction data on the basis of data which has been obtained by averaging a difference between the image data and the delayed image data every unit time, a second correction-data generation circuit for generating second correction data on the basis of data which has been obtained by averaging a difference between the image data and predetermined reference data every unit time, a correction circuit for generating corrected image data by correcting the delayed image data on the basis of the first correction data and the second correction data, and a phase expansion circuit which divides the corrected image data into a plurality of phase-expanded video signals and which feeds the phase-expanded video signals to the plurality of data lines.
In the electrooptic device to which the invention is applied, an image is displayed on the basis of phase-expanded video signals divided into a plurality of channels. In this regard, parasitic capacitances occur in video signal feed lines which lead to the corresponding data lines. Further, parasitic capacitances also occur in the data lines themselves, and pixel capacitors are disposed. Moreover, a distributed resistance exists in a counter electrode. Therefore, differentiator circuits are equivalently formed between the video signal feed lines and the counter electrode, while differentiator circuits are equivalently formed between the data lines and the counter electrode. Accordingly, when the signal level of a video signal which is fed to the electrooptic device changes, a first error voltage is induced in the counter electrode by the differentiator circuit formed between the video signal feed line and the counter electrode. Moreover, when a certain one of the data lines is selected, charging/discharging takes place, so that the second error voltage of the counter electrode changes. Ghosting can be caused by these factors.
According to the first aspect of present invention, the first correction-data generation circuit can average the first difference data every unit time, thereby generating the first correction data, which corresponds to the first error voltage. The second correction-data generation means averages the second difference data every unit time, thereby generating the second correction data, which corresponds to the second error voltage. That is, the first and second correction data correspond to the voltage changes of the counter electrode as predicted. The corrected image data is generated by correcting the delayed image data on the basis of the first and second correction data, so that even when the first and second error voltages occur in the counter electrode, they can be cancelled by generating the video signals on the basis of the corrected image data. As a result, the block ghosting can be greatly reduced and the quality of a displayed image can be strongly enhanced.
In the first aspect of performance of the present invention, the first correction-data generation circuit can preferably include a first subtracter circuit which calculates the difference between the image data and the delayed image data as first difference data, a first averaging circuit which generates first average data obtained by averaging the first difference data every unit time, and a first coefficient circuit which generates the first correction data by multiplying the first average data by a first coefficient.
The first averaging circuit may preferably include an accumulator circuit which accumulates the first difference data every unit time, and a divider circuit which divides the accumulated result by the number of phase-expanded video signals.
In the first aspect of the present invention, the second correction-data generation circuit can include a second subtracter circuit which calculates the difference between the image data and the reference data as second difference data, a second averaging circuit which generates second average data obtained by averaging the second difference data every unit time, and a second coefficient circuit which generates the second correction data by multiplying the second average data by a second coefficient.
The second averaging circuit can include an accumulator circuit which accumulates the second difference data every unit time, and a divider circuit which divides a result of the accumulation by the number of phase-expanded video signals.
Accordingly, the accumulated results are divided by the number of the divided video signals (the number of the phase-expanded video signals), so that the first and second difference data averaged in each block can be calculated.
Preferably, the reference data corresponds to an initial voltage which is applied to pixel capacitors including the pixel electrodes, a counter electrode held opposite to the pixel electrodes, and an electrooptic material.
Alternatively, the reference data may be a precharge voltage which is applied to pixel capacitors including the pixel electrodes, a counter electrode held in opposition to the pixel electrodes, and an electrooptic material.
Since the second error voltage described above is due to the charging/discharging, the changes of the voltages of the data lines and the pixel capacitors become problematic. Therefore, the initial voltage or the precharge voltage can be employed as the reference data. In the actual electrooptic device, however, the optimum value of the reference data can deviate from the initial or precharge voltage on account of various factors, and hence, the reference data may be essentially set so as to visually minimize the block ghosting.
The electrooptic device can further include a plurality of switching elements which sample the respective phase-expanded video signals in accordance with sampling signals and which feed them to the corresponding data lines, and video signal feed lines which feed the respective video signals to the corresponding switching elements. The first coefficient of the first coefficient circuit may preferably be determined on the basis of, at least, parasitic capacitance components due to the respective video signal feed lines and a resistance component of a counter electrode held opposite to the pixel electrodes. Thus, the ghosting attributable to the first error voltage can be effectively cancelled.
The second coefficient of the second coefficient circuit may preferably be determined on the basis of, at least, parasitic capacitance components due to the respective data lines and a resistance component of a counter electrode held opposite to the pixel electrodes. Thus, the ghosting attributable to the second error voltage can be effectively cancelled.
An image processing circuit according to a second aspect of the present invention can include a delay circuit which delays externally supplied image data by a unit time so as to output delayed image data, a first correction-data generation circuit that generates first correction data on the basis of data which has been obtained by averaging a difference between the image data and the delayed image data every unit time, a second correction-data generation circuit that generates second correction data on the basis of data which has been obtained by averaging a difference between the image data and predetermined reference data every unit time and a correction circuit that generates corrected image data by correcting the delayed image data on the basis of the first correction data and the second correction data.
According to the second aspect of the present invention, the first correction-data generation circuit averages the first difference data every unit time, thereby generating the first correction data, which corresponds to a first error voltage. The second correction-data generation circuit averages the second difference data every unit time, thereby generating the second correction data, which corresponds to a second error voltage. That is, the first and second correction data correspond to the voltage changes of a counter electrode as predicted. The corrected image data is generated by correcting the delayed image data on the basis of the first and second correction data, so that even when the first and second error voltages occur in the counter electrode, they can be cancelled by generating video signals on the basis of the corrected image data. As a result, block ghosting can be substantially reduced and the quality of the displayed image can be strongly enhanced.
An electrooptic device according to a third aspect of the present invention can include a plurality of scanning lines, a plurality of data lines, switching elements which are respectively disposed in correspondence with intersections between the scanning lines and the data lines, pixel electrodes which are respectively electrically connected to the switching elements, and a delay circuit which delays externally supplied image data by a unit time so as to output delayed image data. The device can further include a first correction-data generation circuit for generating first correction data on the basis of data which has been obtained by averaging a difference between the image data and the delayed image data every unit time, a second correction-data generation circuit for generating second correction data on the basis of data which has been obtained by averaging a difference between the image data and predetermined reference data every unit time, a correction circuit for generating corrected image data by correcting the delayed image data on the basis of the first correction data and the second correction data, and a phase expansion circuit which divides the corrected image data into a plurality of phase-expanded video signals and which feeds the phase-expanded video signals to the plurality of data lines.
According to the electrooptic device, block ghosting can be substantially reduced and quality of the displayed image can be strongly enhanced.
Preferably, the above electrooptic device may further include a data line driver circuit which generates sampling signals in succession; and a sampling circuit which samples the phase-expanded video signals on the basis of the sampling signals and feeds the sampled signals to the corresponding data lines.
According to this electrooptic device, the quality of the display image can be strongly enhanced, and a time period for which the video signals are fed to the data lines can be lengthened.
Electronic equipment according to the present invention is characterized by including the electrooptic device described above, and includes, for example, a video projector, a notebook-type personal computer, and a mobile telephone.
A a first image data processing method according to a fourth aspect of the present invention is an image data processing method for use in an electrooptic device wherein video signals are fed to a plurality of data lines. The method includes the steps of generating delayed image data by delaying externally supplied image data by a unit time, generating a difference between the image data and the delayed image data as first difference data, generating first average data by averaging the first difference data every unit time, generating first correction data by multiplying the first average data by a first coefficient, generating a difference between the image data and predetermined reference data as second difference data, generating second average data by averaging the second difference data every unit time, generating second correction data by multiplying the second average data by a second coefficient, generating corrected image data by correcting the delayed image data on the basis of the first correction data and the second correction data, and dividing the corrected image data into the plurality of phase-expanded video signals, and then feeding said video signals to the plurality of data lines.
According to this image data processing method, the first correction data corresponds to a first error voltage, and the second correction data corresponds to a second error voltage, so that the first and second correction data correspond to the voltage changes of a counter electrode as predicted. The corrected image data is generated by correcting the delayed image data on the basis of the first and second correction data, so that even when the first and second error voltages occur in the counter electrode, they can be cancelled by generating the video signals on the basis of the corrected image data. As a result, block ghosting can be substantially reduced and the quality of the displayed image can be strongly enhanced.
An image data processing method according to a fifth aspect of the present invention can include the steps of generating delayed image data by delaying externally supplied image data by a unit time, generating a difference between the image data and the delayed image data as first difference data, generating first average data by averaging the first difference data every unit time, generating first correction data by multiplying the first average data by a first coefficient, generating a difference between the image data and predetermined reference data as second difference data, generating second average data by averaging the second difference data every unit time, generating second correction data by multiplying the second average data by a second coefficient, and generating corrected image data by correcting the delayed image data on the basis of the first correction data and the second correction data.
According to this image data processing method, block ghosting can be substantially reduced and the quality of the displayed image can be greatly enhanced.